A programmable logic device, such as a field programmable gate array (FPGA), is designed to be user-programmable so that users can implement logic designs of their choices. In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream into configuration memory cells of the FPGA. As circuit designs implemented in an FPGA are becoming more complex, the number of CLBs, IOBs, and other resources such as multipliers and block RAMs has increased, as well as the generalized routing resources to make the connections between the various blocks.
Clock signals are also used for a variety of purposes in digital circuits, both on board level systems and integrated circuit (IC) devices. An integrated circuit such as a programmable logic device (PLD) typically receives one or more external reference clock signals to generate one or more internal clock signals to operate internal digital circuits. In synchronous systems, global clock signals are used to synchronize various circuits across the board or IC device. For example, internal circuits could be clocked by a first clock signal at a first clock frequency, while input/output (I/O) circuits could be clocked by a second clock signal at a second clock frequency. As the complexity of digital systems increases, clocking schemes continue to become more complicated, and there is a greater need for additional clock signals and more flexibility in generating various clock signals.
While multiple clock generating circuits could be used to generate the multiple clock signals, clock generating circuits typically consume a large amount of chip space. Therefore, most systems use one clock generating circuit to generate a first clock signal called a reference clock signal, and a specialized circuit to derive other clock signals from the reference clock signal. For example, clock dividers are used to generate one or more clock signals of lower clock frequencies from the reference clock signal. Typically, clock dividers divide the frequency of the reference clock signal by an integer value D. Conversely, clock multipliers are used to generate one or more clock signals of higher clock frequencies (e.g. M times the reference clock signal). Combining clock multipliers with clock dividers provides clock circuits which can generate one or more clock signals having frequencies that are fractional values of the frequency of the reference clock signal, commonly called frequency synthesis. For example, if the generated clock frequency has a ratio of M/D that is 7/5 of the reference clock frequency, then the two clock edges should be in concurrence every 7 cycles of the generated clock signal and every 5 cycles of the reference clock signal.
These internal clock signals must be carefully controlled to ensure proper timing in the integrated circuit. Clock management circuits are used in integrated circuits to perform various functions including frequency synthesis. Traditionally, frequency synthesis is done using Phase-Locked Loops (PLLs). A PLL uses a voltage controlled oscillator, which generates a clock signal that approximates the input clock. The control logic, consisting of a phase detector and filter, adjusts the oscillator frequency and phase to compensate for the clock distribution delay. The PLL control logic compares the input clock to a feedback clock and adjusts the oscillator clock until the rising edge of the input clock aligns with the feedback clock. The PLL then “locks.” PLLs typically control the phase and frequency by adjusting an analog voltage. Since using analog voltages increases the sensitivity to noise, fully-digital solutions are attractive for on-chip integration.
Delay-locked loops (DLLs) are also used for frequency synthesis. A delay line of a DLL produces a delayed version of the input clock. The control logic continuously samples the input clock as well as the feedback clock to properly adjust the delay line. Delay lines are constructed either using a voltage controlled delay or as a series of discrete delay elements. A DLL inserts a delay between the input clock and the feedback clock until the two rising edges align, effectively delaying the feedback clock by almost an entire period minus the clock distribution delay. Thus, the DLL output clock compensates for the delay in the clock distribution network, effectively removing the delay between the source clock and its loads.
However, conventional phase locked loops and delay lock loops have a number of disadvantages. Conventional digital control loop architectures do not allow for dynamic frequency transitions with an adaptable bandwidth feature. When employed in programmable logic device, conventional digital control loop architectures would require the programmable logic device to be reconfigured and require the clock synthesizer to relock to a new frequency using an initial locking procedure. That is, a conventional FPGA would not remain active during a frequency transition. Further, conventional digital control loop architectures could not take dynamic control of the frequency.
Conventional digital control loop architectures also do not need adaptive bandwidth acquisition methods because the frequency is not dynamically changed while in use, and therefore, there is no transition phase to accommodate. Conventional frequency synthesis circuits often require clocks in different clock domains to provide course and fine searching to lock to a reference clock. While phase locked loops containing programmable dividers could provide the ability to transition between different frequencies, these systems are analog systems which do not generate a locked output, but merely provide a divided output. Further, the area necessary for an adaptive bandwidth PLL loop filter is excessive. Finally, acquisition and overshoot are traded off in conventional clock management circuits, as in the case of a PLL with a single loop bandwidth during a frequency transition.
As integrated circuits continue to become more complex, there is an ongoing effort to reduce the elements of a given circuit to reduce the overall size of the circuit. Further, the timing of signals generated in an integrated circuit is becoming more complex and the transfer of signals between clock domains is increasing. The circuitry required to transfer multiple signals between clock domains not only takes up more room, but also may lead to timing errors. When sampling frequencies in different time domains, it is often necessary to compare signals in different time domains.
Accordingly, there is a need for an improved circuit for and method of sampling a signal.